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1 march 2013 idt72205lb, idt72215lb, idt72225lb, idt72235lb, idt72245lb idt and the idt logo are registered trademarks of integrated device technology, inc. syncfifo is a trademark of integrated devi ce technology, inc. commercial and industrial temperature ranges ? 2013 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-2766/3 cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 features: ? ? ? ? ? 256 x 18-bit organization array (idt72205lb) ? ? ? ? ? 512 x 18-bit organization array (idt72215lb) ? ? ? ? ? 1,024 x 18-bit organization array (idt72225lb) ? ? ? ? ? 2,048 x 18-bit organization array (idt72235lb) ? ? ? ? ? 4,096 x 18-bit organization array (idt72245lb) ? ? ? ? ? 10 ns read/write cycle time ? ? ? ? ? empy and full flags signal fifo status ? ? ? ? ? easy expandable in depth and width ? ? ? ? ? asynchronous or coincident read and write clocks ? ? ? ? ? programmable almost-empty and almost-full flags with default settings ? ? ? ? ? half-full flag capability ? ? ? ? ? dual-port zero fall-through time architecture ? ? ? ? ? output enable puts output data bus in high-impedence state ? ? ? ? ? high-performance submicron cmos technology ? ? ? ? ? available in a 64-lead thin quad flatpack (tqfp/stqfp) and plastic leaded chip carrier (plcc) ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available ? ? ? ? ? green parts available, see ordering information description: the idt72205lb/72215lb/72225lb/72235lb/72245lb are very high speed, low-power first-in, first-out (fifo) memories with clocked read and functional block diagram input register output register ram array 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 offset register flag logic /( ) read pointer read control logic write control logic write pointer expansion logic reset logic wclk d0-d17 ( )/ rclk q0-q17 2766 drw 01 write controls. these fifos are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (lans), and interprocessor communication. these fifos have 18-bit input and output ports. the input port is controlled by a free-running clock (wclk), and an input enable pin ( wen ). data is read into the synchronous fifo on every clock when wen is asserted. the output port is controlled by another clock pin (rclk) and another enable pin ( ren ). the read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. an output enable pin ( oe ) is provided on the read port for three-state control of the output. the synchronous fifos have two fixed flags, empty ( ef ) and full ( ff ), and two programmable flags, almost-empty ( pae ) and almost-full ( paf ). the offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin ( ld ). a half-full flag ( hf ) is available when the fifo is used in a single device configuration. these devices are depth expandable using a daisy-chain technique. the xi and xo pins are used to expand the fifos. in depth expansion configu- ration, first load ( fl ) is grounded on the first device and set to high for all other devices in the daisy chain. the idt72205lb/72215lb/72225lb/72235lb/72245lb is fabricated using high-speed submicron cmos technology.
2 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 pin configurations plcc (j68-1, order code: j) top view tqfp (pn64-1, order code: pf) stqfp (pp64-1, order code: tf) top view 18 26 19 20 22 23 24 25 21 10 11 12 13 14 15 16 17 56 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 v cc q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 v cc q 6 q 5 gnd q 4 d 14 d 13 d 12 d 11 d 10 d 9 v cc d 8 gnd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2766 drw 02 d 15 d 16 v cc d 17 gnd rclk ren ld oe rs gnd ef v cc q 17 q 16 gnd q 15 pae fl wclk wen wxi v cc paf rxi ff wxo / hf rxo q 0 q 1 gnd q 2 q 3 v cc pin 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d 16 d 17 gnd rclk v cc gnd q 17 q 16 gnd q 15 v cc q 14 q 13 gnd q 12 q 11 v cc q 10 q 9 gnd q 8 q 7 q 6 q 5 gnd q 4 v cc 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 wclk v cc / q 0 q 1 gnd q 2 q 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2766 drw 03
3 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 pin description symbol name i/o description d0?d17 data inputs i data inputs for a 18-bit bus. rs reset i when rs is set low, internal read and write pointers are set to the first location of the ram array, ff and paf go high, and pae and ef go low. a reset is required before an initial write after power-up. wclk write clock i when wen is low, data is written into the fifo on a low-to-high transition of wclk, if the fifo is not full. wen write enable i when wen is low and ld is high, data is written into the fifo on every low-to-high transition of wclk. when wen is high, the fifo holds the previous data. data will not be written into the fifo if the ff is low. rclk read clock i when ren is low, data is read from the fifo on a low-to-high transition of rclk, if the fifo is not empty. ren read enable i when ren is low, and ld is high, data is read from the fifo on every low-to-high transition of rclk. when ren is high, the output register holds the previous data. data will not be read from the fifo if the ef is low. oe output enable i when oe is low, the data output bus is active. if oe is high, the output data bus will be in a high-impedance state. ld load i when ld is low, data on the inputs d0?d11 is written to the offset and depth registers on the low-to-high transition of the wclk, when wen is low. when ld is low, data on the outputs q0?q11 is read from the offset and depth registers on the low-to-high transition of the rclk, when ren is low. fl first load i in the single device or width expansion configuration, fl is grounded. in the depth expansion configuration, fl is grounded on the first device (first load device) and set to high for all other devices in the daisy chain. wxi write expansion i in the single device or width expansion configuration, wxi is grounded. in the depth expansion configuration, wxi is connected to wxo (write expansion out) of the previous device. rxi read expansion i in the single device or width expansion configuration, rxi is grounded. in the depth expansion configuration, rxi is connected to rxo (read expansion out) of the previous device. ff full flag o when ff is low, the fifo is full and further data writes into the input are inhibited. when ff is high, the fifo is not full. ff is synchronized to wclk. ef empty flag o when ef is low, the fifo is empty and further data reads from the output are inhibited. when ef is high, the fifo is not empty. ef is synchronized to rclk. pae programmable o when pae is low, the fifo is almost empty based on the offset programmed into the fifo. the default almost-empty flag offset at reset is 31 from empty for idt72205lb, 63 from empty for idt72215lb, and 127 from empty for idt72225lb/72235lb/72245lb. paf programmable o when paf is low, the fifo is almost-full based on the offset programmed into the fifo. the default offset at almost-full flag reset is 31 from full for idt72205, 63 from full for idt72215lb, and 127 from full for idt72225lb/72235lb/ 72245lb. wxo / hf write expansion o in the single device or width expansion configuration, the device is more than half full when hf is low. in the out/half-full flag depth expansion configuration, a pulse is sent from wxo to wxi of the next device when the last location in the fifo is written. rxo read expansion o in the depth expansion configuration, a pulse is sent from rxo to rxi of the next device when the last out location in the fifo is read. q0?q17 data outputs o data outputs for an 18-bit bus. v cc power +5v power supply pins. gnd ground eight ground pins for the plcc and seven gound pins for the tqfp/stqfp.
4 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 recommended dc operating conditions symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v commercial/industrial gnd supply voltage 0 0 0 v v ih input high voltage 2.0 ? ? v commercial/industrial v il (1) input low voltage ? ? 0.8 v commercial/industrial t a operating temperature 0 ? 70 c commercial t a operating temperature -40 ? 85 c industrial note: 1. 1.5v undershoots are allowed for 10ns once per cycle. symbol rating commercial unit v term terminal voltage ?0.5 to +7.0 v with respect to gnd t stg storage ?55 to +125 c temperature i out dc output current ?50 to +50 ma symbol parameter (1) conditions max. unit c in (2) input v in = 0v 10 pf capacitance c out (1,2) output v out = 0v 10 pf capacitance capacitance (t a = +25 c, f = 1.0mhz) notes: 1. with output deselected, ( oe v ih ). 2. characterized values, not currently tested. idt72205lb idt72215lb idt72225lb idt72235lb idt72245lb commercial and industrial (1) t clk = 10, 15, 25 ns symbol parameter min. typ. max. unit i li (2) input leakage current (any input) ?1 ? 1 a i lo (3) output leakage current ?10 ? 10 a v oh output logic ?1? voltage, i oh = ?2 ma 2.4 ? ? v v ol output logic ?0? voltage, i ol = 8 ma ? ? 0.4 v i cc1 (4,5,6) active power supply current ? ? 60 ma dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c; industrial: v cc = 5v 10%v, ta = -40 c to +85 c) notes: 1. industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. 2. measurements with 0.4 v in v cc . 3. oe v ih, 0.4 v out v cc . 4. tested with outputs disabled (i out = 0). 5. rclk and wclk toggle at 20 mhz and data inputs switch at 10 mhz. 6. for the idt72205/72215/72225 the typical i cc1 = 1.81 + 1.12*f s + 0.02*c l *f s (in ma); for the idt72235/72245 the typical i cc1 = 2.85 + 1.30*f s + 0.02*c l *f s (in ma) these equations are valid under the following conditions: v cc = 5v, t a = 25 c, f s = wclk frequency = rclk frequency (in mhz, using ttl levels), data switching at f s /2, c l = capacitive load (in pf). 7. all inputs = v cc - 0.2v or gnd + 0.2v, except rclk and wclk, which toggle at 20 mhz. absolute maximum ratings notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. i cc2 (4,7) standby current ? ? 5 ma
5 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 ac electrical characteristics (commercial: vcc = 5v 10%, ta = 0c to +70c; industrial: vcc = 5v 10%, ta = -40c to +85c) commercial commercial & industrial (1) idt72205lb10 idt72205lb15 idt72205lb25 idt72215lb10 idt72215lb15 idt72215lb25 idt72225lb10 idt72225lb15 idt72225lb25 idt72235lb10 idt72235lb15 idt72235lb25 idt72245lb10 idt72245lb15 idt72245lb25 symbol parameter min. max. min. max. min. max. unit f s clock cycle frequency ? 100 ? 66.7 ? 40 m h z t a data access time 2 6.5 2 10 2 15 ns t clk clock cycle time 10 ? 15 ? 25 ? ns t clkh clock high time 4.5 ? 6 ? 10 ? ns t clkl clock low time 4.5 ? 6 ? 10 ? ns t ds data set-up time 3 ? 4 ? 6 ? ns t dh data hold time 0 ? 1 ? 1 ? ns t ens enable set-up time 3 ? 4 ? 6 ? ns t enh enable hold time 0 ? 1 ? 1 ? ns t rs reset pulse width (2) 10 ? 15 ? 25 ? ns t rss reset set-up time 8 ? 10 ? 15 ? ns t rsr reset recovery time 8 ? 10 ? 15 ? ns t rsf reset to flag and output time ? 15 ? 20 ? 25 ns t olz output enable to output in low-z (3) 0?0?0?ns t oe output enable to output valid 3 6 3 8 3 12 ns t ohz output enable to output in high-z (3) 3638312ns t wff write clock to full flag ? 6.5 ? 10 ? 15 ns t ref read clock to empty flag ? 6.5 ? 10 ? 15 ns t paf clock to asynchronous programmable almost-full flag ? 17 ? 24 ? 26 ns t pae clock to programmable almost-empty flag ? 17 ? 24 ? 26 ns t hf clock to half-full flag ? 17 ? 24 ? 26 ns t xo clock to expansion out ? 6.5 ? 10 ? 15 ns t xi expansion in pulse width 3 ? 6.5 ? 10 ? ns t xis expansion in set-up time 3.5 ? 5 ? 10 ? ns t skew1 skew time between read clock & write clock forfull flag 5 ? 6 ? 10 ? ns t skew2 (2) skew time between read clock & write clock for empty flag 5?6?10?ns input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 1 ac test conditions figure 1. output load * includes jig and scope capacitances. 30pf* 1.1k 5v 680 d.u.t. 2766 drw 04 notes: 1. industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. all other s peed grades are available by special order. 2. pulse widths less than minimum values are not allowed. 3. values guaranteed by design, not currently tested.
6 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 signal descriptions: inputs: data in (d 0 - d 17 ) data inputs for 18-bit wide data. controls: reset ( rs ) reset is accomplished whenever the reset ( rs ) input is taken to a low state. during reset, both internal read and write pointers are set to the first location. a reset is required after power-up before a write operation can take place. the full flag ( ff ), half-full flag ( hf ) and programmable almost-full flag ( paf ) will be reset to high after t rsf . the empty flag ( ef ) and programmable almost-empty flag ( pae ) will be reset to low after t rsf . during reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. write clock (wclk) a write cycle is initiated on the low-to-high transition of the write clock (wclk). data setup and hold times must be met with respect to the low-to-high transition of wclk. the write and read clocks can be asynchronous or coincident. write enable ( wen ) when the wen input is low and ld input is high, data may be loaded into the fifo ram array on the rising edge of every wclk cycle if the device is not full. data is stored in the ram array sequentially and independently of any ongoing read operation. when wen is high, no new data is written in the ram array on each wclk cycle. to prevent data overflow, ff will go low, inhibiting further write operations. upon the completion of a valid read cycle, ff will go high allowing a write to occur. the ff flag is updated on the rising edge of wclk. wen is ignored when the fifo is full. read clock (rclk) data can be read on the outputs on the low-to-high transition of the read clock (rclk), when output enable ( oe) is set low. the write and read clocks can be asynchronous or coincident. read enable ( ren ) when read enable is low and ld input is high, data is loaded from the ram array into the output register on the rising edge of every rclk cycle if the device is not empty. when the ren input is high, the output register holds the previous data and no new data is loaded into the output register. the data outputs q 0 -q n maintain the previous data value. every word accessed at q n , including the first word written to an empty fifo, must be requested using ren . when the last word has been read from the fifo, the empty flag ( ef ) will go low, inhibiting further read operations. ren is ignored when the fifo is empty. once a write is performed, ef will go high allowing a read to occur. the ef flag is updated on the rising edge of rclk. output enable ( oe ) when output enable ( oe ) is enabled (low), the parallel output buffers receive data from the output register. when oe is disabled (high), the q output data bus is in a high-impedance state. load ( ld ) the idt72205lb/72215lb/72225lb/72235lb/72245lb devices con- tain two 12-bit offset registers with data on the inputs, or read on the outputs. when the load ( ld ) pin is set low and wen is set low, data on the inputs d0-d11 is written into the empty offset register on the first low-to-high transition of the write clock (wclk). when the ld pin and ( wen ) are held low then data is written into the full offset register on the second low-to-high transition of (wclk). the third transition of the write clock (wclk) again writes to the empty offset register. however, writing all offset registers does not have to occur at one time. one or two offset registers can be written and then by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. empty offset register 17 11 0 001fh (72205) 003fh (72215): 007fh (72225/72235/72245) full offset register 17 11 0 default value default value 001fh (72205) 003fh (72215): 007fh (72225/72235/72245) 2766 drw 05 figure 2. write offset register note: 1. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk. figure 3. offset register location and default values note: 1. any bits of the offset register not being programmed should be set to zero. ld wen wclk selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation
7 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 when the ld pin is low and wen is high, the wclk input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. the contents of the offset registers can be read on the output lines when the ld pin is set low and ren is set low; then, data can be read on the low- to-high transition of the read clock (rclk). the act of reading the control registers employs a dedicated read offset register pointer. (the read and write pointers operate independently). a read and a write should not be performed simultaneously to the offset registers. first load ( fl ) fl is grounded to indicate operation in the single device or width expansion mode. in the depth expansion configuration, fl is grounded to indicate it is the first device loaded and is set to high for all other devices in the daisy chain. (see operating configurations for further details.) write expansion input ( wxi ) this is a dual purpose pin. wxi is grounded to indicate operation in the single device or width expansion mode. wxi is connected to write expansion out ( wxo ) of the previous device in the daisy chain depth expansion mode. read expansion input ( rxi ) this is a dual purpose pin. rxi is grounded to indicate operation in the single device or width expansion mode. rxi is connected to read expansion out ( rxo ) of the previous device in the daisy chain depth expansion mode. outputs: full flag( ff ) when the fifo is full, ff will go low, inhibiting further write operations. when ff is high, the fifo is not full. if no reads are performed after a reset, ff will go low after d writes to the fifo. d = 256 writes for the idt72205lb, 512 for the idt72215lb, 1,024 for the idt72225lb, 2,048 for the idt72235lb and 4,096 for the idt72245lb. the ff is updated on the low-to-high transition of the write clock (wclk). empty flag/ ( ef ) when the fifo is empty, ef will go low, inhibiting further read operations. when ef is high, the fifo is not empty. the ef is updated on the low-to-high transition of the read clock (rclk). programmable almost-full flag ( paf ) the programmable almost-full flag ( paf ) will go low when fifo reaches the almost-full condition. if no reads are performed after reset ( rs ), the paf will go low after (256-m) writes for the idt72205lb, (512-m) writes for the idt72215lb, (1,024-m) writes for the idt72225lb, (2,048?m) writes for the idt72235lb and (4,096?m) writes for the idt72245lb. the offset ?m? is defined in the full offset register. if there is no full offset specified, the paf will be low when the device is 31 away from completely full for idt72205lb, 63 away from completely full for idt72215lb, and 127 away from completely full for idt72225lb/72235lb/ 72245lb. the paf is asserted low on the low-to-high transition of the write clock (wclk). paf is reset to high on the low-to-high transition of the read clock (rclk). thus paf is asynchronous. programmable almost-empty flag ( pae ) the programmablealmost-empty flag( pae ) will go low when the read pointer is "n+1" locations less than the write pointer. the offset "n" is defined in the empty offset register. if there is no empty offset specified, the programmable almost-empty flag ( pae ) will be low when the device is 31 away from completely empty for idt72205lb, 63 away from completely empty for idt72215lb, and 127 away from completely empty for idt72225lb/72235lb/72245lb. the pae is asserted low on the low-to-high transition of the read clock (rclk). pae is reset to high on the low-to-high transition of the write clock (wclk). thus pae is asynchronous. write expansion out/half-full flag ( wxo / hf ) this is a dual-purpose output. in the single device and width expansion mode, when write expansion in ( wxi ) and read expansion in ( rxi ) are grounded, this output acts as an indication of a half-full memory. number of words in fifo idt72205lb idt72215lb idt72225lb idt72235lb idt72245lb ff paf hf pae ef 00 0 0 0hhhll 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) 1 to n (1) hh h lh (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 h h h h h 129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1,024-(m+1)) 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1)) hh l hh (256-m) (2) to 255 (512-m) (2) to 511 (1,024-m) (2) to 1,023 (2,048-m) (2) to 2,047 (4,096-m) (2) to 4,095 h l l h h 256 512 1,024 2,048 4,096 l l l h h table 1 ? status flags notes: 1. n = empty offset (default values : idt72205lb n=31, idt72215lb n = 63, idt72225lb/72235lb/72245lb n = 127) 2. m = full offset (default values : idt72205lb m=31, idt72215lb m = 63, idt72225lb/72235lb/72245lb m = 127)
8 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 after half of the memory is filled, and at the low-to-high transition of the next write cycle, the half-full flag goes low and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. the half-full flag ( hf ) is then reset to high by the low-to-high transition of the read clock (rclk). the hf is asynchronous. in the daisy chain depth expansion mode, wxi is connected to wxo of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse when the previous device writes to the last location of memory. read expansion out ( rxo ) in the daisy chain depth expansion configuration, read expansion in ( rxi ) is connected to read expansion out ( rxo ) of the previous device. this output acts as a signal to the next device in the daisy chain by providing a pulse when the previous device reads from the last location of memory. data outputs (q0-q17) q 0 -q 17 are data outputs for 18-bit wide data. , , , , , t t t t rsf rsf rs rsr q 0 - q 17 t rsf = 0 = 1 (1) 2766 drw 06 t rss notes: 1. after reset, the outputs will be low if oe = 0 and tri-state if oe = 1. 2. the clocks (rclk, wclk) can be free-running during reset. figure 4. reset timing (2)
9 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. figure 5. write cycle timing figure 6. read cycle timing wclk d 0 - d 17 t clk t clkh t clkl t ds t ens t dh t enh t wff t wff data in valid no operation rclk skew1 t (1) 2766 drw 07 note: 1. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. if the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk edge. no operation rclk t clk t clkh t clkl t ens t enh t ref t ref valid data t a t olz t oe t ohz q 0 - q 17 wclk skew2 t (1) 2766 drw 08
10 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 notes: 1. when t skew2 minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2*t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary ( ef = low). 2. the first word is available the cycle after ef goes high, always. figure 7. first data word latency after reset with simultaneous read and write figure 8. full flag timing wclk d 0 - d 17 rclk q 0 - q 17 t ds t skew2 t ens t ref t a 0 12 3 d ddd 01 dd (first valid write) t oe t olz t a t frl (1) d 4 t ens 2766 drw 09 note: 1. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. data read wclk d 0 - d 17 rclk q 0 - q 17 t a t wff data write t wff t enh t ens t ds t wff t ds data write next data read t a no write no write data in output register low t skew1 (1) t skew1 (1) t enh t ens 2766 drw 10
11 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 note: 1. when t skew2 minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2*t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary ( ef = low). figure 9. empty flag timing figure 10. write programmable registers wclk d 0 - d 17 rclk q 0 - q 17 t ds t ens t a t skew2 data write 1 data read t enh t ref t ds t ens data write 2 t enh t ref data in output register t frl (1) low 2766 drw 11 t ref t skew2 t frl (1) wclk t clkh t clkl t clk t ens t enh ld wen d 0 ? 15 t ds t dh pae offset paf offset d 0 ? 11 pae offset t ens 2766 drw 12 figure 11. read programmable registers rclk t clkh t clkl t clk t ens t enh q 0 ? 15 pae offset paf offset pae offset unknown t a t ens 2766 drw 13
12 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 figure 12. programmable almost-empty flag timing figure 13. programmable almost-full flag timing wclk t clkh t clkl t ens t enh t ens t pae n + 1 words in fifo n words in fifo rclk t pae 2766 drw 14 wclk t clkh t clkl t ens t enh t ens t paf d ?m + 1 words in fifo memory rclk t paf (1) 2766 drw 15 d ?m words in fifo memory (2) (1) d ?m + 1 words in fifo memory (1) figure 14. half-full flag timing wclk t ens t enh t ens t hf rclk t hf d/2 words in fifo memory (1) 2766 drw 16 d/2 + 1 words in fifo memory (2) d/2 words in fifo memory (1) t clkl t clkh notes: 1. d = maximum fifo depth = 256 words for the idt72205lb, 512 words for the idt72215lb, 1,024 words for the idt72225lb, 2,048 words for the idt72235lb and 4,096 words for the idt72245lb. note: 1. n = pae offset. number of data words written into fifo already = n. notes: 1. m = paf offset. d = maximum fifo depth. number of data words written into fifo memory = 256 - m + 1 for the idt72205lb, 512 - m + 1 for the idt72215lb, 1,024 - m + 1 for the idt72225lb, 2,048 - (m + 1) for the idt72235lb and 4,096 - (m + 1) for the idt72245lb. 2. 256 - m words for the idt72205lb, 512 - m words for the idt72215lb, 1,024 - m words for the idt72225lb, 2,048 - m words for t he idt72235lb and 4,096 - m words for the idt72245lb.
13 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 wclk t ens t clkh t xo note 1 t xo 2766 drw 17 note: 1. write to last physical location. figure 18. read expansion in timing rclk t ens t clkh t xo note 1 t xo 2766 drw 18 rclk t t xi xis 2766 drw 20 note: 1. read from last physical location. figure 16. read expansion out timing figure 15. write expansion out timing figure 17. write expansion in timing wclk t xi t xis 2766 drw 19
14 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 operating configurations single device configuration a single idt 72205lb/72215lb/72225lb/72235lb/72245lb may be used when the application requirements are for 256/512/1,024/2,048/4,096 words or less. these fifos are in a single device configuration when the first load ( fl ), write expansion in ( wxi ) and read expansion in ( rxi ) control inputs are grounded (figure 19). figure 19. block diagram of single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 synchronous fifo note: 1. do not connect any output control signals directly together. figure 20. block diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36 synchronous fifo memory used in a width expansion configuration width expansion configuration word width may be increased simply by connecting together the control signals of multiple devices. status flags can be detected from any one device. the exceptions are the empty flag and full flag. because of variations in skew between rclk and wclk, it is possible for flag assertion and deassertion to vary by one cycle between fifos. to avoid problems the user must create composite flags by anding the empty flags of every fifo, and separately anding all full flags. figure 20 demonstrates a 36-word width by using two idt72205lb/72215lb/72225lb/72235lb/72245lbs. any word width can be attained by adding additional idt72205lb/72215lb/72225lb/72235lb/ 72245lbs. please see the application note an-83. write clock (wclk) write enable ( wen ) read clock (rclk) read enable (ren) load ( ld ) output enable (oe) data in (d) data out (q) full flag ( ff ) programmable ( pae ) half full flag ( hf ) empty flag (ef) programmable (paf) reset ( rs ) 72205lb 72215lb 72225lb 72235lb 72245lb 72205lb 72215lb 72225lb 72235lb 72245lb reset ( rs ) 36 36 18 18 18 18 ff ff ef ef 2766 drw 22 first load ( fl ) read expansion in ( rxi ) write expansion in ( wxi ) write clock (wclk) write enable ( ) read clock (rclk) read enable ( ) load ( ) output enable ( ) data in (d 0 - d 17 ) data out (q 0 - q 17 ) full flag ( ) programmable ( ) half-full flag ( ) empty flag ( ) programmable ( ) reset ( ) idt 72205lb 72215lb 72225lb 72235lb 72245lb 2766 drw 21 first load ( ) read expansion in ( ) write expansion in ( )
15 idt72205lb/72215lb/72225lb/72235lb/72245lb cmos syncfifo tm 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 commercial and industrial temperature ranges march 2013 figure 21. block diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 synchronous fifo memory with programmable flags used in depth expansion configuration load write clock write enable read clock read enable output enable data in data out reset idt 72205lb 72215lb 72225lb 72235lb 72245lb first load ( ) vcc vcc idt 72205lb 72215lb 72225lb 72235lb 72245lb idt 72205lb 72215lb 72225lb 72235lb 72245lb 2766 drw 23 rclk wclk rclk wclk rclk wclk dn qn dn qn dn qn depth expansion configuration ? (with programmable flags) these devices can easily be adapted to applications requiring more than 256/ 512/1,024/2,048/4,096 words of buffering. figure 21 shows depth expansion using three idt72205lb/72215lb/72225lb/72235lb/72245lbs. maximum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load ( fl ) control input. 2. all other devices must have fl in the high state. 3. the write expansion out ( wxo ) pin of each device must be tied to the write expansion in ( wxi ) pin of the next device. see figure 21. 4. the read expansion out ( rxo ) pin of each device must be tied to the read expansion in ( rxi ) pin of the next device. see figure 21. 5. all load ( ld ) pins are tied together. 6. the half-full flag ( hf ) is not available in this depth expansion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together every respective flags for monitoring. the composite pae and paf flags are not precise.
16 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1533 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@idt.com www.idt.com datasheet document history 10/02/2006 pgs. 1 and 16. 10/22/2008 pg. 16. 03/21/2013 pg. 1, 12, 16 xxxxx device type x power xx speed x package x blank clock cycle time (t clk ) speed in nanoseconds process / temperature range 2766 drw24 commercial only commercial (0 c to +70 c) industrial (-40 c to +85 c) i (1) j pf tf plastic leaded chip carrier (plcc, j68-1) thin plastic quad flatpack (tqfp, pn64-1) slim thin plastic quad flatpack (stqfp, pp64-1) 10 15 25 commercial & industrial commercial & industrial lb low power x g (2) green 72205 256 x 18 synchronous fifo 72215 512 x 18 synchronous fifo 72225 1,024 x 18 synchronous fifo 72235 2,048 x 18 synchronous fifo 72245 4,096 x 18 synchronous fifo x blank 8 tube or tray tape and reel notes: 1. industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. all other speed gra des are available by special order. 2. green parts are available. for specific speeds and packages contact your sales office. ordering information

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